The present invention relates to fabrication of transistor devices and, in particular, to such devices which have high breakdown voltages.
Programmable devices, e.g., memory devices, programmable devices, etc., are commonly fabricated using CMOS processing techniques. Often, these techniques include the formation of drain and source regions of a storage element (i.e., a transistor) using a previously created polysilicon gate structure as a mask. When a gate structure is used in this fashion, the resulting drain and source regions of the transistor are said to be self-aligned. That is, the boundaries of the source and drain regions will be aligned to the edge of the polysilicon gate structure which was used as a mask.
In addition to storage elements, i.e., memory cells, however, a programmable device often includes other circuitry such as address decoding circuitry and/or programming circuitry (e.g., in the case of EEPROMs, CPLDs, FPGAs and the like). Some of these peripheral circuits, e.g., those controlling the programming and/or erasing of the storage elements, require transistors capable of withstanding high voltages far in excess of the signal voltages which are otherwise used in the programmable device. For example, a CMOS memory device such as an EEPROM may typically use voltages of 3.3 volts or 5 volts for internal or external signals but may use voltages of 18-20 volts for programming and/or erasing operations. Transistors in the programmable device may be required to block these high voltages at some times and pass them at others. In essence then, these transistors operate as high voltage switches. During such operations the transistors must provide low leakage currents so as not to present increased power consumption for the programmable device as a whole and further to avoid latch up.
For NMOS transistors, a voltage at the drain is blocked when the gate is grounded. In such a scenario, the transistor is off, thus no voltage is passed. However, under these conditions, the gate-drain junction of the transistor is susceptible to breakdown due to several factors. For example, the gate oxide thickness, the junction impurity concentration and the junction depth may all contribute towards the susceptibility of the device to breakdown. Further, if the transistor is formed with self-aligned junctions (as may be the case where such transistors are formed as part of the same processing steps used to create storage elements in a memory device), the risk of breakdown at high voltages is increased. Moreover, the channel width under the gate of the transistor must be of sufficient width to avoid punchthrough. This generally means that high voltage transistors fabricated using self-aligned junction techniques must be relatively large (e.g., on the order of 1.6 xcexcm), consuming valuable die area.
In one embodiment, the present invention provides a single-sided, non-self-aligned transistor which includes a non-self-aligned gate-terminal junction in a substrate and having a relatively thick oxide layer disposed between a gate structure and a terminal region and a relatively thin oxide layer disposed between the gate structure and the substrate. The terminal region may be the drain region of the transistor and it may include a buried N+ region within the substrate. The transistor may be formed in a p-well in the substrate. Further, the transistor may also include a self-aligned gate-terminal junction between the gate structure and a source region.
In a further embodiment, the present invention provides a transistor fabrication method which includes forming an active area in a substrate and implanting an N-type impurity into a first terminal region of the active area. An oxide layer is differentially grown over the active area so that the oxide layer has a first thickness over the first terminal region and a second thickness over the remaining portion of the active area. The first thickness is substantially thicker than the second thickness and, in some embodiments, may be up to twice as thick as the second thickness. A gate structure is formed within the active area, overlapping the oxide layer over the first terminal region. A second terminal region within the active area is then formed adjacent to the gate structure. The first terminal region may be a drain region and the N-type impurity may be Arsenic or Phosphorous or a combination of Arsenic and Phosphorous.
In yet another embodiment of the present invention a memory device may include a non-volatile storage element and a high-voltage transistor. The high-voltage transistor may include a non-self-aligned gate-terminal junction having a breakdown voltage of at least 18 Volts. The gate-terminal junction may be a gate-drain junction and may include a thick oxide layer disposed between a gate structure and a drain region.
The present invention provides a transistor having a reduced size (i.e., pitch) as compared to transistors of the past having a similar breakdown voltage.